1. Field of the Invention
The present invention relates, for example, to an image reproduction apparatus which is a high definition TV receiver for reproducing a high definition TV signal transmitted in MUSE format.
2. Description of Related Art
FIG. 1 is a block diagram showing a configuration of a conventional high definition TV receiver (see "MUSE High Definition TV Transmission System", compiled by the Institute of Electronics, Information and Communication Engineers). In FIG. 1, reference numeral 1 designates an input processing section to de-emphasize a MUSE signal or detect a control signal. The input processing section 1 outputs the processed MUSE signal to a frame memory 2, an interframe interpolation circuit 3, a two-dimensional interpolation circuit 8 and a motion detection circuit 11. The frame memory 2 delays by one frame the video period of the MUSE signal processed by the input processing section 1, and outputs a delayed MUSE signal to the interframe interpolation circuit 3 and the motion detection circuit 11. The interframe interpolation circuit 3 interpolates the signals at the two ends of the frame memory 2 and outputs the signal thus processed to an LPF circuit 4. The LPF circuit 4 subjects the output of the interframe interpolation circuit 3 to 12-MHz low-pass filtering, and outputs the signal thus filtered to a sampling frequency conversion circuit 5. The frequency changer circuit 5 converts the output signal of 32.4-MHz in sampling frequency from the LPF circuit 4 into a 24.3-MHz sampling frequency, and outputs the signal thus converted to a field memory 6 and a 48.6-MHz interfield interpolation circuit 7. The field memory 6 delays the output of the sampling frequency conversion circuit 5 by one field and outputs the delayed signal to the 48.6-MHz interfield interpolation circuit 7. The 48.6-MHz interfield interpolation circuit 7 interpolates the signals at the two ends of the field memory 6 and outputs the resulting signal a mixer circuit 12.
The two-dimensional interpolation circuit 8 two-dimensionally interpolates the signal processed at the input processing section 1 in field dimension, and outputs the processed signal to a sampling frequency conversion circuit 9. The sampling frequency conversion circuit 9 converts the output signal of the two-dimensional interpolation circuit 8 having a sampling frequency of 32.4-MHz to a sampling frequency of 48.6-MHz, and outputs the signal thus converted to the mixer circuit 12. Also, numeral 10 designates a motion detection memory for delaying the video period of the MUSE signal by at least one frame. The motion detection circuit 11 detects a motion area from the outputs of the input processing section 1, the frame memory 2 and the memory 10, and outputs the resulting detection signal to the mixer circuit 12. The mixer circuit 12 mixes the output of the 48.6-MHz interfield interpolation circuit 7 with that of the sampling frequency conversion circuit 9 on the basis of the detection signal from the motion detection circuit 11.
Now, the operation will be explained. The MUSE signal inputted to the input processing section 1 is subjected to such input processings as de-emphasis and control signal detection. The MUSE signal thus subjected to these input processings undergoes separate processings for still and moving images and the resulting signals are mixed at the mixer circuit 12.
First, the still image processing is done in such a manner that the output of the input processing section 1 is delayed by one frame at the frame memory 2, and the signals at the ends of the frame memory 2 are temporally interpolated at the interframe interpolation circuit 3. The signal thus subjected to interframe interpolation has a sampling frequency of 32.4-MHz, but has an aliasing component of at least 12-MHz. In order to remove this aliasing component, the same signal is subjected to low-pass filtering of 12-MHz at the LPF circuit 4. The output of the LPF circuit 4 is converted to 24.3-MHz in sampling frequency at the sampling frequency conversion circuit 6. For conversion from 32.4 MHz to 24.3-MHz, the 32.4-MHz signal is zeroth-order interpolated to 97.2-MHz, and then subsampled at 24.3-MHz. The signal thus frequency-converted to 24.3-MHz is delayed at the field memory 6 by one field. The input and output signals of the field memory 6 are interpolated by the 48.6-MHz interfield interpolation circuit 7. The interfield interpolation requires two-dimensional filtering in view of the reproduction range of the MUSE signal.
In the moving image processing, on the other hand, the signal subjected to input processings at the input processing section 1 is two-dimensionally interpolated at the two-dimensional interpolation circuit 8. The output of the two-dimensional interpolation circuit 8 has a sampling frequency of 32.4-MHz. In order to match this frequency with the final sampling frequency for the still image processing, the output signal of the circuit 8 is converted to 48.6-MHz at the sampling frequency conversion circuit 9. For conversion from 32.4-MHz to 48.6-MHz, in the same way as the processing at the sampling frequency conversion circuit 5, the 32.4-MHz signal is zeroth-order interpolated to 97.2-MHz and subsampled at 48.6-MHz.
The motion detection circuit 11 for mixing the still and moving image processings detects a motion area from the outputs of the input processing section 1, the frame memory 2 and the memory 10 capable of delaying at least one frame. Normally, a motion area is detected by using a one-interframe difference signal subjected to 4-MHz low-pass filtering, a two-interframe difference signal and the same two-interframe difference signal delayed by one frame. Also, a motion vector signal is detected from the control signal multiplexed on the MUSE signal at the input processing section 1, and a dedicated memory is used for horizontal and vertical motion vectors at the motion detection circuit 11, the interframe interpolation circuit 3 and the 48.6-MHz interfield interpolation circuit 7.
On the basis of the motion area information detected by the motion detection circuit 11, the output of the 48.6-MHz interfield interpolation circuit 7 that has undergone the still image processing and the output of the sampling frequency conversion circuit 9 that has undergone the moving image processing are mixed with each other at the mixer circuit 12.
Since the conventional high definition TV receiver (image reproduction apparatus) is configured as described above, the 48.6-MHz interfield interpolation is effected for still image processing. This requires a 12-MHz LPF circuit, a sampling frequency conversion circuit and a 48.6-MHz interfield interpolation circuit, resulting in a bulky circuit. Also, a dedicated frame memory is required for motion vectors.
FIG. 2 is a block diagram showing a conventional image reproduction apparatus for down-converting the MUSE signal to the NTSC signal. (See The Institute of Television Engineers of Japan journal, 1991, Vol. 45, No. 11, "5-2-3" "MUSE-NTSC Down-Converter", written by Yoshiki Mizutani and compiled by The Institute of Television Engineers of Japan.) In FIG. 2, numeral 101 designates an input signal processing circuit for subjecting the MUSE signal to input processing. The input signal processing circuit 101 outputs the MUSE signal thus input processed to a time-axis conversion processing circuit 102 for converting the time axis from MUSE system to NTSC system. The time-axis conversion processing circuit 102 outputs the signal thus converted to a signal separation circuit 103 for separating it to be the luminance signal and the color difference signal from each other. The signal separation circuit 103 outputs the luminance signal (Y signal) to a Y scanning line conversion circuit 104 for converting 1125 scanning lines to 525 scanning lines. The color difference signal is outputted to a time expansion circuit 105 for expanding the time axis by four times. The time expansion circuit 105 outputs the expanded color difference (C) signal to a color-difference vertical filter 106 for matching the expanded color difference signal with the converted Y scanning lines. The output signal of the Y scanning line conversion circuit 104 and the output signal of the vertical filter 106 are outputted to a vertical compression circuit 107 for further compressing the number of the converted scanning lines to 2/3. The output signals of the vertical compression circuit 107, the Y scanning line conversion circuit 104 and the color-difference vertical filter 106 are outputted to an input terminal of a 2-1 selector 108 for selecting one of two signals. The output side terminal of the 2-1 selector 108 is connected to an image processing circuit 109 for processing the converted signal in various ways. The image processing circuit 109 outputs an image-processed digital signal to a D/A converter 110 for converting the digital signal into an analog signal. The luminance signal and the color difference signal are outputted from the D/A converter 110 to a predetermined device.
This conventional system further comprises a 16.2-MHz oscillator 112 as a MUSE system clock, a 14.742-MHz oscillator 113 which is a system clock having a conversion mode capable of maintaining the roundness with a 16:9 monitor (hereinafter referred to as the full mode) and another conversion mode capable of maintaining the roundness by substantially total horizontal conversion with a 4:3 monitor (hereinafter referred to as the wide mode), and a 10.08-MHz oscillator 114 which is a system clock having still another conversion mode capable of maintaining the roundness with a 4:3 monitor by discarding the horizontal conversion(hereinafter referred to as the zoom mode). The output signal of the 16.2-MHz oscillator 112 is outputted to an input signal processing circuit 101 and a time-axis conversion processing circuit 102. The 14.742-MHz oscillator 113 and the 10.08-MHz oscillator 114 are connected to the input side terminal of a 2-1 selector S.sub.18. The output side terminal of the 2-1 selector S.sub.18 is in turn connected to the time-axis conversion processing circuit 102, the signal separation circuit 103, the Y scanning line conversion circuit 104, the time expansion circuit 105, the color-difference vertical filter 106, the vertical compression circuit 107 and the D/A converter circuit 110.
FIG. 3 is a block diagram showing the time-axis conversion processing circuit 102 of FIG. 2. The time-axis conversion processing circuit 102 includes a line decision circuit 116 for outputting a decision signal on an odd- or even-numbered line by detecting lines from the MUSE signal, and time-axis conversion memories 117a, 117b for time-axis conversion from MUSE to NTSC signal. The time-axis conversion memory 117a is supplied with the output signal of the input signal processing circuit 101, an odd-numbered line signal from the line decision circuit 116, the output signal of the 16.2-MHz oscillator 112, and the output signal from the 14.742-MHz oscillator 113 or the 10.08-MHz oscillator 114. The time-axis conversion memory 117a produces Y&R-Y in order an odd-numbered line. The time-axis conversion memory 117b is supplied with the output signal of the input signal processing circuit 101, an even-numbered line signal from the line decision circuit 116, the output signal from the 16.2-MHz oscillator 112, and the output signal of the 14.742-MHz oscillator 113 or the 10.08-MHz oscillator 114. The time-axis conversion memory 117b outputs Y&B-Y in an even-numbered line.
FIG. 4 is a block diagram showing a specific example of the Y scanning line conversion circuit 104 shown in FIG. 2. The Y scanning line conversion circuit 104 includes fixed coefficient multipliers 118a, 118b for multiplying the fixed coefficient of the vertical filter for scanning line conversion and an adder 119.
FIG. 5 is a block diagram showing a specific example of the vertical compression circuit 107 of FIG. 2. The vertical compression circuit 107 includes two line memories 120 for delaying the input signal by one line, five fixed coefficient multipliers 118, adders 119a, 119b, a 2-1 selector S.sub.19, and a vertical compression memory 121. The adder 119a is supplied with a signal from a fixed coefficient multiplier 118, another signal through a line memory 120 and a fixed coefficient multiplier 118, and still another signal through two line memories 120 and a fixed coefficient multiplier 118. These signals are added by the adder 119a. The adder 119b is supplied with a signal through a fixed coefficient, multiplier 118 and another signal through a line memory 120 and a fixed coefficient multiplier 118, and these signals are added by the adder 119b. The adders 119a, 119b are connected to the input, side terminal of the 2-1 selector S.sub.19. The vertical compression memory 121 is connected to the output side terminal of the 2-1 selector S.sub.19.
Now, the operation will be explained. The inputted MUSE signal undergoes such processings as de-emphasis, control signal detection and PLL at the input signal processing circuit 101. The signal thus subjected to input processings is processed along time axis at the time-axis conversion processing circuit 102 shown in FIG. 3. More specifically, the signal thus subjected to input processings is divided into odd- and even-numbered lines and separately inputted to the time-axis conversion memories 117a, 117b. In full or wide mode, for example, the 2-1 selector 108 selects the 14.742-MHz oscillator 113 for converting the system clock to 14.742-MHz. In zoom mode, on the other hand, the 10.08-MHz oscillator 114 is selected to convert the system clock to 10.08-MHz. The signal converted along time axis is separated into the luminance signal and the color difference signal at the signal separation circuit 103. The luminance signal is inputted to the Y scanning line conversion circuit 104, and the color difference signal to the time expansion circuit 105.
With regard to the luminance signal, the Y scanning line conversion circuit 104 converts the number of MUSE effective scanning lines from 1032 to 516. In other words, one scanning line is produced from each two MUSE scanning lines. As shown in FIG. 4, in the Y scanning line conversion circuit 104, the odd- and even-numbered line signals separated by the signal separation circuit 103 and containing only the luminance signal component are inputted to the fixed coefficient multiplier circuits 118a, 118b respectively and multiplied by a predetermined fixed coefficient and added at the adder 119. FIG. 6 is a diagram showing the Y scanning conversion as a model at sampling points. As shown in FIG. 6, one scanning line is produced from each two scanning lines. In the case of FIGS. 4 and 5, the fixed coefficient is 1/2. Although the simplest example was explained above, the vertical filter (Y scanning line conversion circuit 104) for producing 516 scanning lines from 1032 scanning lines may double as a two-dimensional interpolation circuit in some cases in view of the fact that conversion with many scanning lines permits conversion with a minimal aliasing distortion.
The color difference signal is transmitted with the MUSE signal compressed along time axis to 1/4 at the signal separation circuit 103 and therefore is time expanded by four times at the time expansion circuit 105. In case of the block diagram under consideration, two time expansion circuits are required for processing the odd-numbered line color difference signal and the even-numbered line color difference signal separately from each other. The color difference signal thus expanded along time axis is filtered for matching the vertical position with the scanning line of the luminance signal through a color difference signal vertical filter. The color difference signals are transmitted at intervals of 516 scanning lines. Therefore, the scanning lines are not, changed, but each color difference signal is filtered separately to assure vertical phase coincidence between the luminance signal and the color difference signal. The luminance signal converted in scanning lines or the color difference signal whose the vertical phase coinciding with the luminance signal is selected at the 2-1 selector 108, and through the image processing circuit 109, given to the D/A converter 110 in full or zoom mode.
In wide mode, the effective vertical scanning lines are converted to 2/3 by the vertical compression circuit 107. FIG. 7 is for explaining the vertical compression at the vertical compression circuit 107 with reference to a model at sampling points. As shown in FIG. 5, after delaying operation at a line memory 120, a three-line adder 119a and a two-line adder 119b are switched by the 2-1 selector S.sub.19 thereby to produce two scanning lines from three scanning lines. Every signal passing through each line is multiplied by a fixed coefficient at the fixed coefficient multiplier 118. The fixed coefficient of the fixed coefficient multiplier 118 shown in FIG. 5 is the same 1/2 for the lower two units using two lines, while the corresponding figures for the upper three units using three lines are differentiated at 1/4, 1/2 and 1/4 respectively. The effective scanning lines cannot be reduced to 2/3 simultaneously but the vertical conversion to 2/3 can be effected by sequential output of the calculation results after being temporarily stored in the vertical compression memory 121. In the configuration shown in FIG. 2, the circuit of FIG. 5 is required for each of the luminance signal and the color difference signal.
The signals thus converted in full, zoom or wide mode are converted into an analog signal at the D/A converter 110 after undergoing image processing such as contour correction at the image processing circuit 109.
The conventional image reproduction apparatus for down-converting the MUSE signal to the NTSC signal as shown in FIG. 2 is configured as described above. In full and zoom modes, the number of the elective scanning lines of the MUSE signal is converted from 1032 to 516. The monitor for receiving the signal having been converted to the NTSC signal is capable of displaying only 483 lines which is the number of effective scanning lines smaller than 516. As a result, the top and bottom formation on the screen disappear. In wide mode, therefore, another scanning line conversion circuit is required. Further, a scanning line conversion circuit and a vertical filter are required for the luminance signal and the color difference signal respectively, thereby leading to the problem of an increased circuit size.
Also, three memories are required for time-axis conversion and vertical compression. The requirement of two system clock oscillators in full, wide and zoom mode poses the problems not only of a higher cost due to an increased circuit size but also of the adverse effect that high harmonics with a plurality of system clock frequencies and a beat signal have on the TV tuner circuit, etc.